HDCD Decoder

    To many audio enthusiasts, there is no need to introduce Sonore. They make a range of products for audio streaming, signal converters, DACs, and other cool stuff. We worked together on a couple of small projects before and this time we got asked to help with something quite unusual. An HDCD Decoder using one of the legendary decoder chips PMD100. The goal was to design a board that would be able to decode HDCD signal, primarily for archiving purposes.  

    The initial concept was relatively simple. The HDCD chip, data in, data out and we are done. But to make it user friendly and easy to use, we added an SPDIF receiver in software mode, software control for the PMD100 and configuration of various parameters of the PMD100 via DIP switches.  Also, the two channel audio data output from the PMD100 had to be multiplexed and we ended up putting a small FPGA in to do all the control tasks, clock distribution and audio data multiplexing. On top of that the FPGA detects the incoming sample rate, configures deemphasis for the PMD100 and the SPDIF transmitter is in the FPGA as well.  Incoming sampling rate and HDCD stream are indicated via four LEDs. 

    More details can be found in Sonore's discussion thread here: Introducing the Sonore Digital HDCD Decoder. Please contact Sonore if you have any questions regarding this product.

What we did:

• Board architecture design 

• Schematic design and PCB layout

• Samples procurement and manufacturing

• VHDL coding for WM8804 software control, PMD100 software control, sample rate detection, SPDIF transmitter and clock management